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Design Verification (DV) Team Leader – AI Inference Hardware at Ethosia · Trevo
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Job Description
About the role
We are seeking a highly technical, execution-focused Design Verification (DV) Team Lead to architect, lead, and drive the verification ecosystem for our custom AI inference platform. In this role, you will act as a player-coach—combining hands-on testbench development with the leadership needed to guide an agile team of verification engineers through critical block, SoC, multi-die, and pre-silicon tape-out phases.
Your mandate will focus on building robust, scalable verification environments to thoroughly validate high-throughput AI acceleration blocks, complex Network-on-Chip (NoC) architectures, advanced chiplet technologies, and bleeding-edge data center peripherals. Working in a tight-knit startup environment, you will collaborate closely with silicon architects, SoC integration teams, and physical design groups to ensure first-time-right silicon for complex LLM and generative AI workloads at scale.
What you'll do
Technical Leadership & Execution: Lead, mentor, and scale an agile team of DV engineers. Define verification milestones, assign tasks, conduct code reviews, and establish rigorous quality bars to ensure the design meets strict tape-out deadlines.
Verification Architecture & Testbench Development: Maintain a strong hands-on presence by architecting and developing scalable, modular verification environments at both block and top-level SoC stages using UVM (Universal Verification Methodology) and SystemVerilog.
Advanced Interface & Protocol Validation: Drive the strategy to completely verify complex multi-die configurations and next-generation high-speed data center peripherals:
Multi-Die / Chiplet: Validate low-latency, high-bandwidth streaming configurations using UCIe (Universal Chiplet Interconnect Express) or Bunch of Wires (BoW) protocols.
Memory Subsystems: Verify complex interactions with modern memory subsystems including DDR, LPDDR6, LPDDR6x, and HBM.
Coverage Closure & Methodology: Define comprehensive, assertion-based verification (SVA) plans. Drive constrained-random testing, functional coverage definition, and code coverage closure to eliminate architectural and design bugs.
Hardware-Software Verification Alignment: Partner with embedded software and compilation teams to enable early co-verification using emulation platforms or C/C++ reference models to validate true AI workload execution streams.
Requirements
Education & Experience: Bachelor’s or Master’s degree in Electrical/Computer Engineering or a related field, with 7+ years of hands-on ASIC/SoC verification experience, including 2+ years leading or mentoring engineers.
Expert UVM/SystemVerilog Proficiency: Deep architectural mastery of advanced UVM, constrained-random verification, interface checkers, and VIP (Verification IP) integration.
Protocol & Packaging Domain Knowledge: Direct experience verifying complex, high-throughput systems including UCIe, ultra-fast Ethernet (up to 1.6T), PCIe Gen5/6, and high-density memory spaces (LPDDR6/HBM).
AI Compute Cluster Awareness: Strong understanding of verification patterns required for multi-dimensional execution setups (such as matrix-multiplication blocks, tensor units, and asynchronous data paths).
Startup Mentality: Exceptional capability to thrive in a fast-paced startup environment. A pragmatic manager who knows how to balance absolute verification coverage with aggressive commercial tape-out timelines.
EDA Simulation Tools: Advanced familiarity with industry-standard EDA simulation and debug suites (such as Synopsys VCS/Verdi, Cadence Xcelium, or Siemens Questa).