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Job Description
About the role
We are seeking a technical, execution-focused VLSI Team Lead to spearhead the microarchitecture, logic design, and implementation of our custom AI inference acceleration blocks. In this role, you will act as a player-coach—combining hands-on RTL development with the leadership needed to guide a talented group of engineers through critical design and tape-out phases.
Your mandate will focus on driving the execution of high-throughput, low-latency compute engines, advanced memory subsystems, and data path architectures for our ASIC platform. Working in a tight-knit startup environment, you will collaborate closely with software compiler teams, silicon architects, and verification groups to ensure our hardware delivers industry-leading execution for modern LLM and generative AI workloads at scale.
What you'll do
Technical Leadership & Execution: Lead and mentor a small, agile team of front-end VLSI engineers. Define engineering milestones, assign tasks, conduct design reviews, and ensure the team delivers high-quality silicon on schedule.
Microarchitecture & RTL Design: Maintain a strong hands-on presence by architecting and writing clean, synthesizable, high-performance RTL (SystemVerilog) for custom AI accelerator blocks and high-bandwidth interconnects.
Hardware-Software Co-Design: Partner closely with software compiler and embedded software engineering teams to analyze data center workload bottlenecks, using simulation data to refine the microarchitecture for peak compute utilization.
Front-End Ownership: Direct block-level and chip-level frontend integration, including synthesis, linting, clock domain crossing (CDC) analysis, and initial static timing analysis (STA) constraints to optimize Power, Performance, and Area (PPA).
Cross-Functional Alignment: Coordinate closely with the Design Verification (DV) team to review test plans, close coverage metrics, and triage complex debug scenarios to guarantee first-time-right silicon.
Requirements
Education & Experience: Bachelor’s or Master’s degree in Electrical/Computer Engineering or a related field, with 7+ years of hands-on ASIC/IC design experience, including 2+ years of experience leading or mentoring engineers.
Expert RTL & Microarchitecture: Advanced proficiency in SystemVerilog/Verilog for high-performance, complex digital design, with a proven track record of delivering blocks that successfully went to tape-out.
AI & Data Center Domain Knowledge: Strong understanding of execution patterns used in AI inference (e.g., matrix-multiplication blocks, vector units, tensor engines, pipelined data paths, and advanced caching/scratchpad structures).
IP & Interconnect Integration: Experience integrating custom compute blocks with industry-standard subsystems (e.g., high-speed memory interfaces like HBM/DDR, PCIe interfaces, or RISC-V/ARM complexes).
Startup Mentality: Exceptional capability to thrive in a fast-paced startup environment. A pragmatic manager who knows how to balance technical excellence with aggressive delivery timelines.
EDA Tool Ecosystem: Deep familiarity with industry-standard EDA frontend tools (Synopsys, Cadence, or Siemens) for simulation, synthesis, and timing closure.