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Design Verification Lead – Peripheral IP - Haifa, Israel at Qualcomm · Trevo
Company
Qualcomm Israel Ltd.
Job Area
Engineering Group, Engineering Group > ASICS Engineering
General Summary
Qualcomm’s Peripheral IP organization is looking for a hands‑on Design Verification Lead to drive verification of next‑generation wired/wireless peripheral subsystems that power Snapdragon platforms.
As a DV Lead in the Peripheral group, you will own verification of complex IPs and subsystems, define and execute UVM‑based verification strategy, and lead a small team of talented engineers to first‑time‑right silicon.
What you'll do
Define verification strategy, test plan, and coverage goals for complex peripheral IP and subsystem blocks
Architect, develop, and maintain UVM‑based constrained‑random verification environments
Lead day‑to‑day activities of a small DV team: task planning, code and testplan reviews, mentoring, and technical guidance
Drive debug of complex issues across RTL, testbench, and system level, working closely with design, emulation and validation teams
Debugging complex failures in large‑scale regressions
Scripting (Python/Perl/Tcl/shell) in a UNIX/Linux environment
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
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Nice to have
Experience with high‑speed peripherals (e.g., USB, PCIe, Display, SerDes, or similar I/O IP)
Knowledge of low‑power, reset, and clock‑domain interactions at IP/SoC level
Familiarity with regression management, metrics, and sign‑off criteria
Experience working with global, cross‑site teams
What We Offer
Opportunity to own verification of cutting‑edge peripheral IP used in high‑volume products
A strong technical environment with the ability to lead, influence, and mentor
Collaboration with world‑class design, architecture, CAD and validation teams
Growth path toward broader technical or managerial leadership within Qualcomm
If you are a technically strong verification engineer with deep UVM experience and the drive to lead people and projects, we’d like to hear from you.
To apply: Please submit your CV through the Qualcomm careers portal and reference “DV Lead – Peripheral IP Group” in your application.