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Test Engineer, Senior - Hod Hasharon at Qualcomm · Trevo
Company
Qualcomm Israel Ltd.
Job Area
Engineering Group, Engineering Group > ASICS Engineering
General Summary
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.
What you'll do
In this position, you will define, develop & characterized analog and digital test modules which will be integrated into a production test program of both wafer level and final test.
The key important experience we are seeking for is a proven skill of evaluating design specifications/datasheet into a ATE test definition while closely collaborating with the VLSI teams (Arch, Design/DFT, Back-end, SW, HW, Verification).
In the next stage, apply the test definition into a high quality and reliable ATE test module via coding, debug, validation, characterization, provide a feedback report and support the mass production ramp.
As part of the ATE test development, you will define and design ATE HW (Load Boards & Probe Cards), optimized on High-Speed SerDes Testing, analyses and evaluates component specification versus performance.
The job requires to work independently with company stakeholders as well as our vendors & partners. The job requires travelling to our vendors sites, within and outside Israel.
What You’ll Need
B.Sc. degree in Electrical/Computer engineering or Computer Science
Collaborate with different teams (including VLSI, backend, HW engineering, Quality & Reliability, vendors)
ATE test development experience at least 5 years or equivalent experience.
Hands-on experience with Advantest/Teradyne testers
Pre-si DFT for production definition, pattern generation, conversion, and virtual testing
Post-Si TP characterization and qualification, bringing TP to production quality.
Technical prowess in design for test and High-Speed SerDes IPs testability will be an advantage.
About You
Multi-tasking capabilities
High self-learning skills
High execution quality standards
An innovative approach to problem solution
References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
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Requirements
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.