NextSilicon

NextSilicon's primary product line is the Maverick series of HPC processors, built on an internally developed Reconfigurable Dataflow Architecture (RDA). This architecture differs fundamentally from both standard CPUs and from NVIDIA-style GPU architectures: rather than applying a fixed computation model to all workloads, Maverick dynamically reconfigures its dataflow graph at runtime to match the specific computation pattern of the application being executed. The result, as demonstrated in early benchmark data shared with pilot customers, is substantially higher utilization of on-chip compute resources and lower energy consumption per floating-point operation for the targeted class of workloads.

The specific problem NextSilicon addresses is the performance bottleneck experienced by workloads that are not embarrassingly parallel. NVIDIA's GPU architecture, built around the SIMD (Single Instruction, Multiple Data) model, excels when all processing units execute the same operation on different data simultaneously. However, a significant class of HPC workloads — including molecular dynamics simulations, computational fluid dynamics, financial risk model optimization, and plasma physics simulations — exhibit irregular memory access patterns and variable branching behavior that lead to low GPU utilization. Maverick is engineered specifically for this class.

NextSilicon's target customers are organizations running large-scale HPC workloads: US government national laboratories (such as those operated under the Department of Energy), defense agencies requiring high-performance scientific computation, quantitative finance firms running large-scale Monte Carlo and risk simulations, and pharmaceutical and biotech companies requiring molecular modeling at scale. The buying audience is senior technical leadership — Heads of HPC, VP Engineering, and CTO-level executives at research-intensive organizations — and the market is exclusively enterprise, with no SMB or individual-developer segment.

NextSilicon sells exclusively through a direct sales model with long enterprise sales cycles typical of the semiconductor and HPC hardware markets. The company engages prospective customers through a structured evaluation program in which a pilot system is deployed in the customer's environment and benchmarked against existing infrastructure. There is no self-serve purchase option, and the product is not available on any cloud marketplace or through channel resellers as of late 2025.

NextSilicon's pricing is not publicly disclosed. Given the nature of the product — a bespoke hardware accelerator deployed in enterprise and government environments — contracts almost certainly include hardware acquisition, multi-year support agreements, and professional services for workload porting and optimization. There is no subscription, per-seat, or per-API-call pricing model applicable to a physical accelerator of this type.

NextSilicon's primary technical moat lies in two areas: first, the patented Reconfigurable Dataflow Architecture itself, which took multiple years of fundamental research to develop and cannot be easily replicated; and second, the compiler and runtime software stack built on top of LLVM that manages the dynamic reconfiguration of the chip's dataflow graph. Building a production-quality compiler for a novel reconfigurable processor is a multi-year undertaking requiring rare expertise in both compiler theory and hardware microarchitecture — expertise that NextSilicon has concentrated in Tel Aviv.

The engineering organization works day-to-day on RTL design and verification using SystemVerilog, physical design using industry-standard EDA tools, LLVM-based compiler development targeting the Maverick instruction set architecture, low-level runtime software including Linux kernel drivers and scheduling infrastructure, and application engineering that ports and optimizes real customer workloads (molecular dynamics codes, CFD solvers, quantitative finance engines) to run on the Maverick platform.

The Maverick processor is NextSilicon's sole named product. It is an HPC accelerator built on the Reconfigurable Dataflow Architecture (RDA) that the company developed internally over multiple years beginning in 2017. Maverick is designed to be inserted into existing HPC cluster environments as a drop-in accelerator node, working alongside conventional CPUs and interconnected via standard high-speed fabrics. The chip includes a substantial on-chip memory hierarchy designed to support the irregular memory access patterns that characterize scientific workloads, and executes computation using a dataflow execution model rather than a traditional von Neumann fetch-decode-execute pipeline.

Because NextSilicon operates with a single-product focus, there is no distinction between a flagship product and adjacent or acquired products. All engineering resources, from silicon design through compiler development and application engineering, are directed at Maverick. The company has not made any acquisitions, and no externally developed technology has been integrated into the product line under a different product name.

The most recent significant product milestone on the public record is the disclosure of Maverick's architecture in 2022, which included the first publicly available technical details about the reconfigurable dataflow model. In 2023, early customer evaluation programs began. As of late 2024 and through 2025, NextSilicon has not announced a second-generation Maverick by name, though given the standard semiconductor development cadence and the Series B funding received in January 2022, internal work on subsequent silicon generations is expected to be underway.

No products have been officially sunset. Given the company's age and single-product focus, early internal silicon tape-outs prior to the commercial Maverick served as learning vehicles and toolchain development platforms, but these were never marketed to external customers and their discontinuation is not a commercial sunset event.

Maverick is a physical hardware product and therefore does not appear on AWS Marketplace, Snowflake Native Apps, or Salesforce AppExchange. Integration at the software level is expected to involve standard HPC job schedulers such as Slurm and workload managers compatible with the broader HPC ecosystem, as well as support for common scientific computing programming frameworks. The company has invested in tooling that reduces the barrier for developers familiar with standard HPC programming models to port their workloads to Maverick.

NextSilicon has not publicly announced SOC 2, FedRAMP, ISO 27001, or other software-centric compliance certifications. However, given that the company is working with US defense and government clients on pilot programs, it is reasonable to infer that applicable hardware security and supply-chain compliance frameworks are in progress. No certification has been officially confirmed as of late 2025.

The most prominent direct competitor to NextSilicon is NVIDIA Corporation, whose H100 and H200 GPU accelerators currently dominate both AI training and large portions of the HPC accelerator market. The key structural difference between the two is that NVIDIA's CUDA-based GPU ecosystem excels at embarrassingly parallel workloads with regular memory access patterns, while NextSilicon's Maverick is explicitly designed for the subset of HPC workloads where GPU utilization falls below economically acceptable thresholds due to irregular computation graphs. NextSilicon is not competing with NVIDIA across the full AI training market; it is carving out a performance niche where NVIDIA's architecture is weakest.

Intel is a second meaningful competitor, particularly through its Gaudi 2 and Gaudi 3 accelerators — products designed to offer an alternative to NVIDIA for AI training at lower cost. Intel's Gaudi line is optimized for transformer-based AI model training and inference, and while it overlaps with NextSilicon in the sense of being an alternative to GPU for compute-intensive tasks, it addresses a fundamentally different workload class. The legacy Intel Xeon Phi (Knights Landing generation) attempted to serve HPC scientific computing and was discontinued in 2020, leaving a gap in the market that NextSilicon is positioning Maverick to fill.

Graphcore, a Bristol-based company that developed the Intelligence Processing Unit (IPU) for AI workloads, is a third competitor in the broader accelerator space. Graphcore raised over $700 million between 2016 and 2021, achieved a peak valuation of $2.8 billion, but struggled to achieve commercial scale. In 2024, SoftBank acquired Graphcore. The distinction between NextSilicon and Graphcore is significant: Graphcore was primarily positioned as an AI/ML accelerator competing with NVIDIA in neural network training, whereas NextSilicon targets general-purpose scientific HPC workloads with non-AI-specific computation patterns.

NextSilicon does not appear in Gartner Magic Quadrant or Forrester Wave reports, as both of those analyst frameworks focus on enterprise software categories rather than semiconductor hardware. HPC-specific analyst coverage from Hyperion Research and IDC positions NextSilicon as an emerging player in the reconfigurable computing segment, with the caveat that commercial scale has not yet been demonstrated at the level of NVIDIA or even Graphcore at their peak.

NextSilicon's pricing positioning is clearly premium. The product is targeted at buyers for whom performance per watt and total cost of ownership over a multi-year HPC infrastructure lifecycle justify a significant upfront investment. There is no free tier, no community edition, and no price-competitive positioning against commodity server hardware. The company competes on technical merit, not on price.

In 2023, reports emerged indicating that NextSilicon had secured a pilot engagement with a US defense-related organization, though the specific agency and contract value were not publicly disclosed. This is consistent with the company's stated focus on the national laboratory and defense computing market in the United States. No other named customer wins or losses have been officially disclosed.

The trajectory for NextSilicon is one of a niche deepener: the company is not attempting to win the mass accelerator market, but rather to establish a dominant technical position in a specific class of HPC workloads where no well-capitalized incumbent is currently focused. Sector tailwinds include the rapidly rising cost of data center electricity, which is pushing operators to seek higher compute-per-watt efficiency; the growth of computational biology and pharmaceutical simulation workloads; and the US government's sustained investment in domestic HPC infrastructure through programs such as the Exascale Computing Project. The primary headwind remains the entrenched NVIDIA CUDA ecosystem, which has trained an entire generation of HPC developers on a single programming model and creates significant switching friction.

NextSilicon has neither been acquired nor made acquisitions of its own as of late 2025.

NextSilicon's sole Israeli location is in Tel Aviv, which functions as the company's global R&D headquarters. There is no publicly documented presence in Herzliya, Haifa, Beer Sheva, Petah Tikva, or Jerusalem. The Tel Aviv office hosts essentially the entire engineering organization, making Israel the unambiguous technical center of gravity for the company.

The Israel headcount exceeds 150 employees, with functions encompassing the full engineering lifecycle: VLSI design (RTL and physical design), design verification, compiler engineering, runtime and system software, and application engineering. Finance, legal, and administrative functions in Israel are modest in scale. The New York office handles business development, sales, and customer engagement, with no significant engineering presence outside of Israel.

NextSilicon has not publicly announced any expansion, downsizing, or relocation of its Israeli offices during 2023 or 2024. Headcount growth has been measured and selective, consistent with the reality that chip design engineering talent — particularly engineers with experience in reconfigurable architectures and LLVM-based compiler development — is globally scarce and cannot be hired at the pace of a software company scaling a sales organization.

Both co-founders are Israeli. Barak Shoshany, who serves as CEO, has a background in computer architecture and VLSI from his service in IDF technical units and subsequent industry experience. Erez Nisan, who serves as CTO, brings deep expertise in chip design and hardware-software co-design from his own IDF technical unit background. Virtually all of the senior technical leadership at the company are Israeli, reflecting the founding team's network and the depth of Israel's chip design engineering talent pool.

In Israel, NextSilicon typically hires for the following roles: RTL Design Engineers with experience in SystemVerilog and chip microarchitecture; Physical Design Engineers with ASIC back-end and timing closure experience; Verification Engineers proficient in UVM and formal verification; Compiler Engineers with deep LLVM knowledge and experience targeting novel ISAs; System Software Engineers for driver development and runtime infrastructure; and Application Engineers who can port and optimize scientific codes written in C, C++, and Fortran. These are uniformly senior, specialist roles requiring five or more years of experience, and the company does not typically hire fresh graduates for core engineering positions.

Notable investors who participated in NextSilicon's funding rounds include Horizons Ventures (the family office of Hong Kong billionaire Li Ka-shing), Atreides Management, and Corner Ventures, all of whom participated in the January 2022 Series B of $80 million. The Israeli Innovation Authority (formerly the OCS — Office of the Chief Scientist) provided early-stage support to NextSilicon, consistent with its mandate to fund deep-tech R&D in Israel. No named Israeli strategic partners — such as Israeli system integrators, defense contractors, or technology companies — have been publicly announced.

NextSilicon's organizational culture is strongly engineering-driven, with recruitment heavily oriented toward graduates of elite IDF technology units — particularly Unit 8200 and Mamram — where experience in low-level systems programming, hardware-software interfaces, and complex systems architecture is developed. The company also recruits M.Sc. and Ph.D. graduates in Electrical Engineering and Computer Science from the Technion – Israel Institute of Technology in Haifa and from Tel Aviv University, since the theoretical depth required to design a novel processor architecture extends beyond what most industry backgrounds alone can provide. The combination of IDF unit alumni and advanced academic credentials is the defining demographic of NextSilicon's Tel Aviv engineering floor.