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Job Description
What you'll do
End-to-End System Definition: Define the holistic, system-level specifications for AI inference servers and rack deployment form-factors, harmonizing mechanical, electrical, thermal, firmware, and software requirements.
Hardware-Software Co-Design: Collaborate intensely with silicon architects, compiler teams, and cloud-software developers to optimize workload execution pipelines. Define software abstraction layers, runtime behaviors, and driver boundaries that match the physical memory constraints and compute structures of the hardware.
Bleeding-Edge HW Architecture Definition: Drive the architectural boundaries for multi-layer PCBs and multi-chip modules, ensuring optimal configurations for ultra-high-speed interfaces:
Power & Liquid Thermal System Definitions: Architect high-power density infrastructure parameters, specifying multiphase voltage regulator modules (VRMs) running at ultra-low core voltages (<0.8V). Define system mechanical boundaries for direct-to-chip liquid cooling assemblies and cold plate layouts.
Tier-1 & Ecosystem Management: Lead technical alignment and hand-off specifications with Tier-1 server and rack manufacturers (e.g., Foxconn, Quanta, Supermicro, Wiwynn). Author crisp, rigorous Hardware/Software Interface (HSI) documents and system integration guides.
Validation & Compliance Strategy: Blueprint full-stack system validation plans, specifying how early emulation models, post-silicon bring-up, thermal profiling, and AI workload benchmarks must interact to guarantee deployment-ready stability.
Key Requirements & Qualifications
Education & Experience: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a highly related field, with 7+ years of cross-disciplinary hardware/software systems engineering experience specifically within server, cloud, or enterprise data center platforms.
True Full-Stack HW/SW Fluency: A proven career history that successfully spans both worlds:
Hardware Domain: Deep architectural knowledge of high-speed SerDes, power delivery networks (PDN) for hundreds of amps, signal/power integrity rules, and liquid cooling mechanics.
Software Domain: Solid grasp of deep learning compilation frameworks (e.g., Triton, TVM), kernel-level drivers, memory layout orchestration, and distributed data center execution patterns (Kubernetes, Ray).
Tier-1 Server & Cluster Infrastructure Experience: Direct experience working closely with Tier-1 server ODMs on high-density system integration, board-to-board topologies, power management, and server rack-level infrastructure scaling.
Protocol & Standards Mastery: Deep engineering knowledge of modern data center specifications, notably PCIe Gen6/7, Ethernet fabrics up to 1.6T, LPDDR6/6x, and Open Compute Project (OCP/OAM) deployment architectures.
Startup Agility & Execution: Exceptional capability to thrive in a fast-paced, high-ambiguity startup environment. A pragmatic architect who can balance ultimate technical ideals with aggressive product commercialization windows.