Participate in the Architecture definition and exploration
Own and lead Micro-architecture development
Complete advanced Verilog/SV coding using advanced methodologies/procedures/AI tools.
Participate in the Verification convergence of the RTL and demonstrate full accountability to the Design code
Meet production ready quality from both Front End (functional and formal verification) and Back End perspective (Timing closure and Static Timing Analysis) within the project timeline.

B.Sc. / M.Sc. in Electrical Engineering (recent graduate).
Basic understanding of VLSI / ASIC / verification concepts (academic level is sufficient).
Fluent English – mandatory for daily collaboration with global teams.
Strong motivation to learn and grow in VLSI Digital Design domain

PerlVerilogAzureCloudGenAIAIDevOpsEmbeddedASICGit