TriEye is a deep tech company turning scientific breakthroughs into transformative sensing and electro optical capabilities. Built on cutting edge research in nanophotonics, semiconductors, and advanced optics, we develop proprietary technologies that push beyond the limits of conventional sensing, enabling systems to see, detect, understand, and act in ways that were previously impractical or impossible.
At the core of our technology is a new approach to SWIR sensing, enabled by our breakthrough CMOS based platform. But our innovation extends far beyond the sensor itself. By combining advanced semiconductor design, nanophotonics, proprietary laser and illumination technologies, computational sensing, and deep system level engineering, we create tightly integrated solutions with fundamentally new capabilities, not simply better performance or lower cost.
This full stack approach allows TriEye to rethink sensing from the physics up, translating advances at the material and device level into meaningful advantages at the system and application level.
We are looking for some exceptional talent to join our Chip Design team as a Senior Layout Designer.
Your Day to Day
Take ownership of the physical implementation of our pixel, tackling the unique challenge of fitting complex circuitry into an extremely small area while working within tight routing and metal-layer constraints.
Develop and optimize pixel layouts with careful attention to area, matching, parasitics, connectivity, reliability, and manufacturability.
Build and integrate large pixel arrays with the surrounding analog circuitry, including bias circuits, row drivers, test structures, and other supporting blocks.
Take responsibility for the physical integration and layout verification of the complete large-scale analog block, ensuring it is clean and ready for delivery to top-level chip integration.
Work closely with analog, device, digital, and outsource companies to solve implementation challenges and translate circuit and system requirements into robust silicon
Collaborate with the fab on technology-related topics and the development and integration of special devices
BSc or PE in Electrical Engineering or Computer Engineering
At least 8 years of experience in analog/mixed-signal layout design
Experience with Cadence layout tools and flows
Deep understanding of physical verification processes and methodologies, including DRC, LVS, ANT, ERC & DFM
Strong knowledge of common analog layout techniques and design practices
Strong problem-solving skills, attention to detail, and ability to work independently
Excellent communication and cross-functional collaboration skills
Fluent in English, both verbal and written
Why should you be a TriEyoneer?
Work at the edge of what’s possible
Turn scientific breakthroughs in sensing, photonics, and semiconductors into capabilities that were previously impractical or impossible.
Build what others can’t
Work across physics, hardware, software, and algorithms to build complex systems from first principles and take them all the way to real world deployment.
See your work make an impact
Build technology that moves beyond the lab into demanding real world applications across defense, robotics, industrial, and emerging markets.
Grow with exceptional people
Join a multidisciplinary team that values ownership, curiosity, technical excellence, and pushing boundaries together.
Enjoy the journey
Modern offices in Tel Aviv with easy access to public transport, plus a competitive benefits package including gym, parking, Cibus, generous vacation, and team events.
General statement
TriEye is an equal-opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.
Nice to have
Experience in integration of large analog/mixed-signal layout blocks and taking them through physical verification to top-level integration — an