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Senior Director, Silicon Architecture and Design Engineering (Ethernet) at Altera · Trevo
Job Details:
Altera is seeking a Senior Director, Silicon Architecture and Design Engineering (Ethernet) to serve as our Ethernet Center of Excellence leader, owning the technical direction, architecture, methodologies, and multi-generation Ethernet roadmap across Altera’s programmable device portfolio. The role is Altera’s technical authority for Ethernet across business units, leading a global silicon team.
The ideal candidate brings deep expertise in Ethernet and networking silicon across multiple product generations, plus a track record of leading large silicon organizations and complex development programs, and will shape silicon strategy and execution for FPGA, SoC, and platform technologies supporting AI, cloud, networking, and edge applications.
What you'll do
Lead, grow, and mentor a high-performing silicon engineering organization delivering complex FPGA, ASIC, and SoC products across Altera’s programmable portfolio.
Own end-to-end silicon execution from product definition and microarchitecture. Managed RTL, verification, DFT, emulation, implementation, bring-up, and validation teams.
Define and drive Ethernet architecture across MAC, PCS, FEC, Auto-Negotiation, Link Training, and high-speed PHY/SerDes integration for current and future product generations.
Represent Altera externally with hyperscale, networking, and AI infrastructure customers, ecosystem partners, and standards bodies (IEEE 802.3, Ultra Ethernet Consortium, OIF), translating that engagement into Ethernet IP requirements and reference designs.
Provide technical leadership for networking datapath architecture, including packet processing, L2/L3 forwarding, QoS, traffic management, buffering, scheduling, congestion management, and telemetry.
Drive large, complex silicon programs: planning, resource alignment, milestone tracking, and risk management against aggressive performance, quality, cost, and schedule targets.
Partner with architecture, software, systems, product planning, and manufacturing to turn product requirements into executable silicon roadmaps, and represent silicon engineering in executive reviews.
Lead cross-functional decisions on architectural tradeoffs, hard/soft IP partitioning, and internal-versus-third-party Ethernet IP strategy across throughput, latency, bandwidth, congestion behavior, PPA, cost, manufacturability, and schedule.
Engage foundry, IP, and EDA partners, and drive methodology, automation, and KPI-based improvements in quality, predictability, and velocity.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$231,500 - $341,075 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
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Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science, and 15+ years in silicon engineering, ASIC, SoC, or FPGA product development.
10+ years in networking and Ethernet technologies, including architecture, silicon development, or product development for networking, switching, interconnect, or data center infrastructure.
Deep expertise in IEEE 802.3 Ethernet architecture, from MAC/PCS through high-speed PHY/SerDes integration.
Experience with multiple generations of high-speed Ethernet through 800G-class, plus AI/data center scale-out networking (RDMA/RoCE, lossless Ethernet, congestion control, or Ultra Ethernet).
10+ years leading or working across the silicon development lifecycle, from architecture and RTL through verification, DFT, emulation, physical design, post-silicon validation, and production.
Nice to have
Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
Experience leading silicon development at advanced process nodes, delivering high-complexity SoCs or ASICs into production, and standing up new teams.
Experience with emerging 1.6T Ethernet and 112G/224G-class SerDes, and with FPGA or heterogeneous SoC platforms, including Ethernet IP, transceiver integration, and third-party PHY/controller IP.
Job Type:
Regular
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.