RFIC Designer

Altair is a leading provider of cellular IoT chipsets and solutions, enabling connected devices across industries such as automotive, industrial, healthcare, smart metering, asset tracking, and consumer electronics. Our technology powers reliable, low-power connectivity for millions of devices worldwide. At Altair, the people are the heart of our company. We're a team of engineers, builders, and problem-solvers who take ownership from day one. You'll work closely with experienced teammates, contribute to real decisions, and see your impact from concept through delivery. We maintain a flat organization where ideas flow freely between engineers and leadership, and experienced team members actively mentor newer colleagues. What you will be doing Join our Silicon Design team as an RFIC Designer and play a central role in developing advanced RF circuits and subsystems using cutting-edge CMOS technologies. You’ll take full ownership - from interpreting system requirements and selecting topologies, through transistor-level design, layout guidance, validation, and production ramp-up.. Working closely with system, layout, backend, and validation teams, you’ll take on a hands-on, multidisciplinary role developing innovative RF solutions that directly contribute to next-generation wireless communication technologies. We’re looking for a hands-on RFIC designer who has taken RF and analog blocks from transistor-level design all the way to working silicon. You should be equally comfortable running simulations in Cadence, discussing system-level trade-offs across the RF signal chain, and debugging silicon in the lab. Success in this role means owning your blocks end to end and working closely with system, layout, and validation teams to deliver designs that meet performance goals. On a typical day On a typical day, you might start by reviewing simulation results for an LNA or mixer block, join a system-level discussion to align on how performance budgets are allocated across the RF signal chain, review layout floorplanning with the layout team to make sure parasitics won’t compromise performance, and spend the afternoon in the lab measuring silicon and debugging unexpected results together with the validation team.