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Senior System and Chip Architect at Ethosia · Trevo
More fit checks, tailored CVs, and complete prep for every role.
Job Description
What you'll do
Define and own the architecture for key subsystems of Axonica's AI inference SoC — compute fabric, memory hierarchy, interconnect, and I/O from concept through tape-out.
Translate brain-inspired and novel compute paradigms into concrete microarchitecture, working closely with algorithm and AI research teams to keep the hardware faithful to the underlying computational model.
Lead architecture-level tradeoff analysis across power, performance, area (PPA), memory bandwidth, and latency, and defend those tradeoffs with data.
Design, build, and use performance and power simulation models (C++, SystemC, or Python) to explore the architecture design space and validate decisions before RTL exists.
Use AI-assisted tools and workflows to accelerate specification writing, design-space exploration, and architecture testing and validation.
Mentor other architects and engineers as the architecture team grows.
Requirements
7+ years of experience in system or chip architecture for AI/ML accelerators, GPUs, DSPs, CPUs, or other high-performance compute silicon, at a company that has shipped production silicon (e.g., NVIDIA, NextSilicon, Intel, AMD, Mobileye/Habana, Anapurna/AWS, Google, Broadcom, or similar).
Proven, hands-on experience architecting chips from a clean sheet — defining novel microarchitecture and system design from first principles, not simply integrating existing IP or cores — with a track record of taking that architecture through to tape-out, more than once.
Deep fundamentals in computer architecture: pipelines, memory hierarchies, interconnect/NoC design, and dataflow or non-von-Neumann compute architectures.
Highly desired understanding of AI/ML workloads — DNN and transformer inference, quantization, sparsity — and how algorithmic choices map to hardware efficiency and power.
Skilled in defining and building architecture-level simulation models — performance, power, or cycle-approximate — to explore design tradeoffs and validate decisions ahead of RTL.
Experience using AI-assisted or AI copilot tools to define architecture specifications and to test and validate architecture, both functionally and for performance.
Comfort working across the algorithm/hardware boundary, partnering closely with RTL, verification, and software/compiler teams.
A BSc or MSc in Electrical Engineering, Computer Engineering, Computer Science, or a related field (PhD a plus).
Excellent communication skills and the judgment to operate with high autonomy in a fast-moving, early-stage environment.
Nice to have
Experience with near-memory or in-memory compute, HBM, Flash, or other advanced memory technologies aimed at breaking the memory wall.
Prior experience as a founding or early architect at a hardware startup.