Extensive experience in RTL design (Verilog/SystemVerilog) for control logic, Datapath, memory subsystems, and specialized processing units.

Strong understanding of digital architecture, including pipelining, arbitration, memory hierarchy, and system-level integration.

Proficiency in functional verification, including testbench development, assertions, coverage metrics, and debugging (UVM experience is a plus).

Familiarity with ASIC and FPGA design flows, including synthesis, timing closure, and DFT.

Comfortable working across the full hardware stack — from architectural specification and microarchitecture to physical implementation support.

Pay and benefits

Competitive cash compensation, with package based on location and experience

Flexible Work setting, no strict office requirement

Spacious office in Central Area with a Gym

Option for a relocation & bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location.

Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers).

Healthcare coverage (including family-friendly options), pension contributions, Keren Hishtalmut

Professional development support and 20 days of PTO, in addition to public holidays.

A high-paced, multicultural (with 9 nationalities), and engineering-led environment.

Hardware Design Engineer

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