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Senior Signal Integrity Engineer (Hands-on) at Intel · Trevo
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Job Description
About the role
Job Details:
Intel Central Engineering Group (CEG) team delivers best-in-class Ethernet products and is at the heart of Intel's transformation from a PC company to a company that powers the cloud and billions of smart, connected computing devices. CEG's compelling Ethernet products move the world's data and are the foundations of cloud service and telecommunications data centers. You will be exposed to High-Speed I/O protocols such as PCIeGen6-7, DDR5-6, and PAM4 Ethernet 224Gb, which are a part of our Ethernet Infrastructure Processing Unit (Intel IPU) and Foundation NIC (FNIC) Ethernet product lines. We propose a dynamic and flexible workplace position, working directly with highly capable design, system, and pre/post-silicon teams within the organization.
Most of the team's engineers have 10+ years of experience, and we are looking for a highly skilled multidisciplinary engineer with proven experience in Signal Integrity engineering to lead the hardware design of our next division projects' challenges and be part of Ethernet networking's accelerated growth.
In this position, as a signal integrity engineer, you will be responsible for modeling channel elements in 3D and 2D EM simulation tools for pre- and post-layout stages of package and platform design for PCIe, Ethernet, and memory interfaces. You are expected to have a thorough understanding of RF circuits and electromagnetic wave propagation; the role includes learning the specifications of each interface and the required design limitations that should be verified.
You will be expected to lead all signal integrity activities related to multiple projects for various high-speed and low-speed interfaces utilizing traditional and automated tools. You will work closely with silicon design teams and Hard IP vendors and will be responsible for the model's correlation based on cross-section and electrical measurements at the post-manufacturing stage and modeling manufacturing variation impact on the channels. You will be responsible for running the sign-off simulation flows for various designs, providing feedback to the design teams, and being hands-on in the lab for experiments when required. You would also be responsible for identifying/qualifying new AI-based automation techniques and solutions and providing technical leadership to working groups/task forces through debugging and reviews.
B.Sc./M.Sc. Electrical Engineer with over 7 years of relevant experience in Signal Integrity
Proven design experience in the semiconductor ASIC development industry is a MUST
Proven planning and design flow buildup
Proven experience with PCB technology and layout techniques (Analog and Digital) including stack-up, routing, and advance SI/PI consideration
Proven hands-on experience with EDA tools: HFSS, CST, ADS, Simbeor, or equivalent
Knowledge of CAD tools: Cadence Allegro or Mentor Expedition, or equivalent
Proven experience with modeling and simulation one of the Ethernet, PCIe, DDR interfaces
Familiar with layout technics
Working experience with AI-based tools
Lab hands-on experience in high-speed, low-speed, and clocks circuitry signals measurement such as high-end Oscilloscopes, VNA, TDR, BERT's, etc.
Excellent debugging skills, ability to analyze problems, diagnose the root cause and apply corrective actions
Ability to work as a team player and contribute in a cross-functional product team on a daily basis
Strong verbal and written communication skills in English for interacting with design, evaluation and production engineers; customers; technical marketing engineers; and program managers
Job Type:
Experienced Hire
Shift:
Shift 1 (Israel)
Primary Location:
Israel, Petah-Tikva
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.