Verification Engineer

A groundbreaking Deep-Tech startup operating in the High-Performance Computing (HPC) space, designing next-generation adaptive compute architectures for supercomputers and advanced data centers. The company's proprietary technology drastically accelerates highly complex compute workloads across AI, Aerospace, Biotech, Energy, and Defense applications. Founded by seasoned entrepreneurs and backed by hundreds of millions in top-tier venture capital, the company employs over 300 top-tier engineers globally. Located in Tel Aviv, operating on a hybrid work model. Role Description- • Joining as a Senior Verification Engineer owning end-to-end ASIC / Chiplet Verification processes for core hardware product components. • Building complex, high-performance UVM Verification environments from scratch, defining verification strategies, test plans, and coverage goals. • Developing constrained-random testbenches using SystemVerilog, defining Functional Coverage, Code Coverage, and System Assertions (SVA). • Working hands-on with industry-standard ASIC simulation, emulation, and debugging tools. • Collaborating closely with Architecture, Logic Design (RTL), and System teams to ensure silicon quality and robustness. Requirements- • 5 years of hands-on experience as an ASIC / System-on-Chip (SoC) Verification Engineer – Mandatory • Deep, proven proficiency in SystemVerilog for verification – Mandatory • Hands-on experience with constrained-random verification, Functional Coverage, and Assertions – Mandatory • Proven background in building UVM environments from scratch – Significant Advantage • B.Sc. in Electrical Engineering, Computer Engineering, or Computer Science – Advantage