Physical Design Manager

Description NextSilicon is reimagining high-performance computing (HPC & AI). Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. We have developed a novel software-defined hardware architecture that is achieving significant advancements in both the HPC and AI domains. At NextSilicon, everything we do is guided by three core values: Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance. Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard. Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide. At NextSilicon, we are reimagining high-performance computing. Our pioneering coprocessor vastly accelerates supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research. NextSilicon is looking for a talented and experienced Physical Design lead to take part in the physical design and help lead the company’s BE activities . This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the company’s design efforts and will have a significant influence on our final product Requirements 7+ years of physical design experience, working on complex subsystems Experience in leading BE projects, subsystems and or complex high speed blocks Experience in leading people (technical and or managerial ) Experience working in advanced node implementation flows Good Knowledge of physical design industry standards and practices, including physically aware synthesis, floor planning, CTS, place and route. Good understanding and experience in physical design verification methodology for debugging LVS and DRC issues at chip and block level Proficiency in power delivery, signal integrity, advanced packaging, power projection, and design for low dynamic power Working knowledge of extraction and STA methodologies and tools Good capabilities of scripting languages, such as Perl, Python and Tcl Responsibilities Lead blocks and sub systems execution from RTL to GDSII. Clearly reflect status and execution metrics and help identify and solve execution bottlenecks. Spec and define full floor plan, including pin placement, partitions, and power grid Develop and validate high-performance, low-power clock network guidelines Perform critical block-level place and route and create designs that meet PPA targets. Review the vendors’ physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations Work with vendors on defining physical design methodologies and assist in flow development for chip