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Microchip AES Design team in Bangalore is looking for an experienced and motivated Design-For-Test Principal Engineer to provide test
hardware solution for various microchip Business units. As a member of test development team, you will be responsible for understanding the
existing DFT test structures and clock strategy used across multiple business units and provide architectural improvements to improve test
coverage. The candidate should have experience with ATPG and MBIST. The candidate should have in depth knowledge of Tessent/Modus
tool execution.
Requirements
Hands on expertise on handling DFT on hierarchical designs.
Should have good post silicon DFT bring-up and debug experience.
Should have a good knowledge of simulation debug and prior experience at SoC level.
Excellent written and verbal communication skills.
Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.
Experience:
Bachelors/Masters in Electronics or equivalent degree with 9+ years of experience
Travel Time:
0% - 25%
To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.