Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
As a Sr. Principal Program Manager, ASIC Design at Astera Labs, you will own the cross-functional execution framework for advanced ASIC programs from early planning through tapeout. You will drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams.
You will partner closely with architecture, RTL design, functional verification, emulation, DFT, synthesis, physical design, CAD, IP, product management, engineering leadership, and external partners.
This is a high-impact role for a technical program leader who can operate in a fast-moving environment, manage ambiguity, drive accountability, and establish scalable execution practices across complex silicon development programs.
What you'll do
Program Execution & Planning
Lead pre-silicon execution of complex ASIC and subsystem programs from concept through tapeout.
Own program plans, schedules, milestones, dependencies, risk registers, dashboards, and executive-level status reporting.
Drive pre-silicon and NPD phase-gate execution from kickoff through final GDS handoff, ensuring cross-functional readiness across architecture, RTL, verification, DFT, physical design, signoff, and tapeout.
Cross-Functional Alignment & Coordination
Drive cross-functional alignment across architecture, RTL design, verification, emulation, DFT, synthesis, physical design, CAD, IP integration, product management, and external partners.
Track IP delivery, PDK updates, CAD/EDA flow readiness, tool dependencies, and foundry requirements.
Partner with Post-Silicon PM and Validation teams to absorb feedback from post silicon bring up, including bug reports and Si issues.
Risk Management & Decision-Making
Identify execution risks, lead risk mitigation plans, and drive trade-off decisions across scope, schedule, resources, and quality.
Communicate program health, risks, dependencies, and decisions clearly to engineering teams, senior leaders, executives, and external partners.
Process & Operational Excellence
Establish scalable program management practices, operating rhythms, decision forums, documentation standards, and communication mechanisms, lead constant improvement.
Basic Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
10+ years of experience in ASIC/SoC development or silicon program execution, including 3+ years in technical program management, engineering program management, or technical leadership.
Experience managing pre-silicon ASIC development flows, including architecture planning, RTL design, functional verification, synthesis, DFT, physical design, timing closure, signoff, and tapeout.
Experience with advanced process nodes and high-performance ASIC/SoC development.
Strong understanding of ASIC development milestones from product requirements through final GDS handoff.
Familiarity with EDA flows, CAD infrastructure, IP integration, PDK readiness, foundry requirements, and vendor dependency management.
Experience with pre-silicon validation platforms such as simulation, emulation, FPGA prototyping, or hardware/software co-validation.
Experience driving complex cross-functional programs with multiple engineering teams, technical dependencies, external vendors, and aggressive schedules.
Nice to have
Strong technical judgment with the ability to manage trade-offs across performance, power, area, cost, schedule, quality, and risk.
Excellent communication, organizational, leadership, and stakeholder-management skills.
Ability to influence without authority across global, cross-functional, and cross-cultural teams.
Ability to operate independently in a fast-paced, ambiguous, high-growth environment.
Experience with high-speed connectivity, SerDes, PHY, PCIe, CXL, Ethernet, networking, switching, or AI infrastructure silicon.
Salary range is CAD 195,000 to CAD 240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.