About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell's Test Solutions Engineering (TSE) organization is seeking an experienced HSIO Test Solutions Engineering Lead to help define how next-generation silicon products are tested from architectural concept through high-volume manufacturing.
TSE drives pre-silicon test strategy, DFT requirements, manufacturing test planning, and test chip validation. Partnering closely with Design, Validation, Product Engineering, and Test Engineering teams, TSE ensures products are architected for testability and equipped with the coverage, observability, and diagnostics required for successful product introduction, manufacturing ramp, and long-term quality.
Working at the forefront of advanced SerDes, chiplet, die-to-die, and mixed-signal technologies, you'll help solve some of the industry's most challenging test and characterization problems while influencing products long before they reach production.
What You Can Expect
What you'll do
Define Test Strategy and DFT Architecture
Develop test strategies and DFT requirements for advanced HSIO technologies.
Influence product testability, observability, and diagnostics during architecture and design phases.
Drive test planning and validation for next-generation SerDes, chiplet, and die-to-die architectures.
Lead Test Chip and Silicon Validation
Define and execute validation strategies for test chips and first-silicon bring-up.
Characterize IP and subsystem functionality across voltage, frequency, and temperature conditions.
Correlate validation results with manufacturing test requirements.
Enable Manufacturing Readiness
Develop production screening methodologies and manufacturing test plans.
Collaborate with Product Engineering and Test Engineering teams to enable production deployment.
Analyze production data and drive improvements in quality, yield, and test efficiency.
Drive Technical Leadership
Partner with Architecture, Design, DFT, Validation, Product Engineering, Reliability, and Manufacturing teams.
Lead cross-functional reviews and influence key technical decisions.
Mentor engineers and contribute to next-generation test methodologies and best practices.
Expected Base Pay Range (USD)
138,400 - 204,800, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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Requirements
BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, Physics, or related field.
10+ years of experience in semiconductor Test Engineering, Product Engineering, DFT, Silicon Validation, or related disciplines.
Strong understanding of semiconductor manufacturing, yield analysis, and qualification methodologies.
Demonstrated ability to lead complex cross-functional technical initiatives.
Experience in one or more of the following areas:
High-speed SerDes technologies (56G, 112G, 224G and beyond)
PCIe, CXL, UCIe, or die-to-die interfaces
Design-for-Test (DFT)
Silicon validation and debug
Automated Test Equipment (ATE)
Production test development
Mixed-signal characterization and correlation
Nice to have
MS or PhD in Electrical Engineering, Computer Engineering, or related field.
Experience with Advantest 93K and/or Teradyne UltraFLEX platforms.
Experience with advanced packaging, chiplets, and heterogeneous integration technologies.
Experience supporting AI, networking, cloud, or data center products.
Python, automation, analytics, or test infrastructure development experience.