FPGA Design Engineer

Description Quantum Machines is a global leader in control systems for quantum computing, a field on the verge of exponential growth. Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands. At the core of QM lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers. Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field. We are looking for a hands-on FPGA Design Engineer, specialized in high-performance digital design and FPGA-based system development, as part of the QM-Platform team. This role involves ownership of FPGA interfaces and connectivity logic, including high-speed communication blocks, platform integration, and close collaboration with embedded and hardware teams. You will work on complex FPGA/SoC platforms, enabling robust and scalable solutions for quantum control systems. Responsibilities Own the design and implementation of FPGA-based interfaces such as PCIe, I2C, SPI, and high-speed GT communication. Develop and integrate FPGA logic on advanced platforms, including Xilinx UltraScale+ and Versal. Collaborate closely with embedded, hardware, and system teams to ensure seamless HW/SW/FPGA integration. Drive FPGA bring-up, debugging, and validation at both lab and system levels. Participate in system architecture definition and cross-team design decisions. Requirements Must-Haves 3+ years of experience in FPGA design and digital system development. Strong proficiency in Verilog/SystemVerilog RTL design. Hands-on experience with Xilinx FPGA families (UltraScale+, Zynq, or Versal). Experience implementing and debugging high-speed interfaces (PCIe, Ethernet, JESD, or similar). Solid understanding of FPGA development flows, including synthesis, place & route, and timing closure. Experience with lab debugging tools (e.g., ILA/ChipScope, oscilloscopes, logic analyzers). Experience with simulation and verification methodologies (RTL and gate-level). Strong problem-solving skills and attention to detail. B.Sc. or higher in Electrical Engineering, Computer Engineering, or equivalent. Strong communication skills and ability to collaborate across teams. Advantages Experience with Versal architecture, including NoC design and integration. Background in ASIC design or verification. Familiarity with FPGA backend flows and static timing analysis (STA). Scripting experience (Python, TCL, Makefile) and/or C/C++ knowledge.