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Senior EDA Design Automation Engineer - Digital Implementation at Intel · Trevo
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Job Description
About the role
Job Details:
What you'll do
We are seeking an EDA Tools Hardware Engineer to develop and enhance cutting-edge engineering design automation tools, methodologies, and workflows. In this role, you will drive the enablement of next-generation hardware design tools and flows, directly contributing to improved efficiency, power, and performance optimization for advanced technology nodes. Your expertise will support the seamless adoption and advancement of EDA technologies, ensuring Intel remains at the forefront of innovation in silicon design.
Business Group
The Intel Foundry business group is dedicated to delivering world-class silicon design solutions through collaboration with technology development teams. This group focuses on driving Design Technology Co-Optimization (DTCO), enabling foundational IPs (FIPs), Process Design Kits (PDKs), and reference flows. These efforts empower Intel's design ecosystem and ensure scalability, efficiency, and cutting-edge innovation, aligning with the company's broader goal of technological leadership in advanced silicon and packaging technologies.
Architect and implement EDA tool flows for Digital Implementation and Sign Off design flow, digital and analog design, spanning front-end and back-end processes from RTL to GDS.
Execute disciplined flow development and delivery to meet tight milestones for advanced technology nodes.
Collaborate with external EDA vendors on enabling reference flows optimized for Intel technology platforms.
Develop and verify hardware designs, integrating design components into hierarchical systems to ensure end-to-end tool testing coverage.
Enhance tools, scripts, and platforms to optimize productivity, power, and performance outcomes.
Analyze and refine methodologies to improve design automation processes for technology transitions and new node enablement.
Build deep expertise in areas such as digital design, verification, layout, full-chip integration, clocking, and timing, and apply these insights to future design flow enhancements.
Provide strategic input on industry trends in EDA and drive transformative initiatives for hardware design environments.
Requirements
Bachelor's, Master's or PhD degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or a related field.
For candidates with a Bachelor's degree: Minimum of 8 years of experience in the development of EDA tools, flows, or design environments for digital or analog designs.
Proficiency in EDA tools and workflows, including expertise in physical design flows, IP integration, and packaging technologies.
Strong AI and programming skills with experience in UNIX scripting languages (e.g., Python, Perl, TCL).
Familiarity with design flow automation, source control management systems, cloud infrastructure, and compute allocation.
Nice to have
Demonstrated ability to understand and interpret industry trends in EDA and align tool initiatives with advanced technologies.
Familiarity with automated SoC design methodologies and analog/mixed-signal design workflows, (Eg. Cadence Genus, Innovus).
Experience in deploying new features for revision control systems, continuous integration, and design data management.
Exceptional analytical, debugging, and problem-solving abilities, coupled with strong communication skills.
Join us in shaping the future of silicon design and innovation. Your expertise and contributions will be at the heart of delivering impactful technologies that redefine possibilities at Intel.
Job Type:
Experienced Hire
Shift:
Shift 1 (Malaysia)
Primary Location:
Malaysia, Penang
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.