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Senior Silicon DFT Lead, Google Cloud at Google · Trevo
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Job Description
About the role
In most instances, this position requires in-person interviews as part of the hiring process.
What you'll do
Lead and execute DFT activities in the design, implementation, and verification of solutions for Application-Specific Integrated Circuits (ASICs).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self-Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage DFT team planning and deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project: planning, execution, tracking, quality, and sign-off.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Nice to have
Bachelor's degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
10 years of experience in Design for Test (DFT) from architecture to post-silicon production support.
4 years of experience with people management.
Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and industry tools, DFT and Physical Design flows, and DFT verification flow.
Experience in leading DFT activities throughout the whole ASIC development flow.
Master's degree in Electrical Engineering, or a related field.
Experience in post-silicon Debug, test or product engineering.
Experience in JTAG and iJTAG protocols and architectures.
Experience in SoC cycles, silicon bring-up, and silicon debug activities.
Knowledge of fault modeling techniques.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will play a crucial role in DFT design and supporting devices to production. You will be responsible for providing technical leadership in DFT, as well as developing flows, automation, and methodology throughout the project life-cycle.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.