Job Details:
About Altera
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
As a Physical Design Engineer at Altera, you will play a critical role in our backend implementation flow — from RTL/netlist through to GDSII/tape-out for FPGA/SoC devices. You will interface with architecture, logic design, DFT, CAD/EDA, and manufacturing teams to achieve our performance/power/area (PPA) goals, with particular emphasis on programmable logic structures, block and full-chip integration, and the unique demands of FPGA technologies (e.g., configurable logic blocks, routing fabrics, I/O rings, on-chip power domains).
What you'll do
Lead and execute physical design implementation tasks (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist → GDSII.
Apply PPA optimization techniques (performance / timing closure, power reduction, area efficiency) across blocks or full-chip hierarchies.
Collaborate with front-end design, architecture, CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets and DFT Insertions are met.
Develop and improve physical design flows, methodologies, scripts and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR and reduce manual intervention.
Participate in timing, power, EM/IR integrity, signal/power noise, DRC/LVS/ERC verification and sign-off readiness.
Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization.
Work closely with manufacturing and packaging partners to ensure implementation is manufacturable (DFM/DFY), meets yield targets and meets high-volume production requirements.
Debug physical design issues, interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds.
Mentor and collaborate with junior engineers; contribute to reviews, documentation of flows, and continuous process improvement.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$149,100 - $215,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
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Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline with 10+ years of industry experience in physical design, physical implementation, or SoC backend design, including the following:
10+ years of hands-on experience in digital ASIC and/or SoC physical design, including synthesis, floorplanning, place-and-route, clock tree synthesis (CTS), routing, engineering change order (ECO) implementation, and signoff.
8+ years of experience using industry-standard EDA implementation and signoff tools such as Synopsys IC Compiler II, Synopsys Fusion Compiler, Cadence Innovus, Cadence Encounter, Synopsys PrimeTime, Synopsys StarRC (STAR-RCX), Mentor Calibre, or equivalent tools.
5+ years of scripting and automation experience using Tcl for physical design flow development and automation.
2+ years of experience using Python, Perl, Shell, or similar programming languages to improve physical design productivity and workflow automation.
8+ years of experience with physical design methodologies including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, engineering change orders (ECOs), and physical signoff.
5+ years of experience implementing low-power design methodologies including clock gating, multi-power domain implementation, power intent, and power-aware physical design.
5+ years of experience performing static timing analysis and timing closure for high-speed ASIC or SoC designs.
3+ years of experience performing power integrity analysis, IR drop analysis, electromigration (EM) analysis, signal integrity analysis, and recommending corrective actions.
5+ years of experience working with physical verification and signoff activities including DRC, LVS, ERC, DFM, and related manufacturing verification flows.
5+ years of experience collaborating with front-end RTL, architecture, CAD/EDA, manufacturing, packaging, and DFT teams throughout the physical implementation lifecycle.
3+ years of experience performing chip integration activities including physical block integration, pin assignment, timing and constraint push-down, and hierarchical implementation.
2+ years of experience with bump planning, redistribution layer (RDL) routing, MiM capacitor planning, ESD signoff, or advanced package-aware physical implementation.
2+ years of experience performing I/O budgeting and implementation across chip-, partition-, and block-level physical designs.
Nice to have
Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
Experience in advanced semiconductor process technologies including 7nm, 5nm, or below.
Experience with FPGA or programmable logic device physical implementation flows.
Familiarity with FPGA architectures including programmable routing fabrics, configurable logic blocks (CLBs), on-chip interconnect, I/O rings, and static or dynamic reconfiguration.
Experience with low-power design methodologies including power grid design, power gating, multi-voltage domain implementation, UPF/CPF, and power signoff methodologies.
Experience with full-chip integration flows and block-to-chip convergence.
Experience achieving timing closure for high-frequency semiconductor designs operating at 1 GHz or greater.
Experience working in high-volume semiconductor manufacturing environments with DFM, DFY, reliability, and yield optimization considerations.
Experience mentoring junior engineers or providing technical leadership for physical implementation of complex design blocks.
Experience with AI/ML-assisted physical design optimization tools or methodologies, including Synopsys DSO.ai, Fusion Compiler AI, Cadence Cerebrus, or similar technologies.
Job Type:
Regular
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.