Job Details:
Intel is seeking an experienced Logic Design engineer for the Intel Chassis Group, which is chartered to deliver the chassis for SoCs within Intel. The role involves logic design of component and foundation IPs which can be used to build an SoC chassis. The ideal candidate will have strong design and Verilog skills and some background in protocol conversion bridges for AMBA/CXL protocols. Understanding of concepts such as QoS, access control, flow control, debug, RAS, security and error handling is a plus.
What you'll do
Develop logic designs, register transfer level (RTL) coding, and simulations required for functional units, IP blocks, and subsystems.
Define and implement architecture and microarchitecture features for the interconnect IP block and sub-system which includes high-performance data plane and control plane routers, switches, arbiters, protocol conversion bridges, debug/trace components, and clock and power controls.
Perform rigorous quality checks and optimization of RTL designs to improve IP power, performance, area, and timing, ensuring delivery of high-quality IP.
Evaluate design trade-offs across area, bandwidth, timing, and reliability to achieve balanced and efficient IP functionality.
Support Sub-system/SoC customers with high-quality IP integration and verification workflows.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with a minimum of 7 years of experience in logic design and RTL development.
Proficiency in hardware description languages, including Verilog and System Verilog.
Strong knowledge of digital design principles, such as timing analysis, power optimization, and area trade-offs.
Experience with industry-standard EDA tools for design, Quality checks and simulation (e.g., Synopsys, Cadence, Mentor Graphics).
Communication skills
Capacity to work across large, geographically distributed engineering teams across multiple time zones.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Nice to have
Familiarity with AMBA (CHI, AXI, AHB, APB) and PCIe/CXL protocols is a plus
Experience in working with architecture, verification, SoC integration teams
Good understanding of PPA trade-offs
Ability to work with physical design to solve timing issues
Experience with use of AI to assist logic design is a plus