About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Central Engineering – Optical PHY (CE-OPHY) team designs high-speed and optical transceivers for communication infrastructure in long-haul, metro and datacenter. We address the bandwidth, capacity and power issues faced by cloud computing, mega data centers that powers the social media giant platforms. Our innovative approaches have resulted in the company’s products being first to market in many of key areas, developing the most advanced chips and subsystems solutions to address the ever-increasing demand of higher data rates driven by video-on demand, gaming and other real time data streams. We are seeking talented individuals to work on solving technical challenges with the most outstanding group of collaborators in the industry.
Join our team of experts and make a difference in an exciting career opportunity. As a member of a dynamic CE-OPHY team, the candidate will be responsible for designing circuits used for high-speed optical transceivers. The member will have an opportunity to work in deep submicron process and collaborate with the team on next-gen high-speed optical transceivers.
The position is located at our office in Pavia, Italy, and requires full-time on-site presence
What You Can Expect
You will play a key role in developing high-performance analog or DSP- based transceivers operating in the multi-tens of GHz range, utilizing advanced CMOS nodes (3nm and beyond).
Analyze block specifications and select appropriate topologies
Design analog blocks at the transistor level
Supervise layout activities, provide guidelines and conduct post-layout verifications
Model blocks and validate models
Collaborate with other teams to enhance existing solutions
Train and mentor junior designers