About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As a Principal, Digital IC Design Engineer at Marvell, you will join the DCE – Connectivity Business Group, the team developing the high performance connectivity silicon that underpins AI scale data centers for the world’s leading hyperscalers. Our group architects and implements advanced digital pipelines, high speed datapaths, and DSP driven processing engines that enable ultra high bandwidth, low latency data movement across next generation Ethernet and optical interconnects. You’ll work closely with experts in architecture, verification, physical design, and systems to deliver complex ASICs that integrate cutting edge DSP algorithms, robust protocol handling, and PHY level innovations. This role offers the opportunity to shape foundational connectivity technologies, drive technical direction, and contribute to silicon solutions powering the global AI infrastructure.
What You Can Expect
Collaborate with systems and architecture teams to define SoC‑level specifications, including performance, power, area, feature requirements, and DSP/datapath architectural considerations.
Translate high‑level product and protocol requirements into detailed micro‑architecture specifications for complex subsystems, high‑speed datapaths, DSP pipelines, and IP blocks.
Own RTL development for assigned blocks, delivering high‑quality, synthesizable SystemVerilog RTL that meets functionality, performance, and power targets.
Implement and drive the full ASIC front‑end design flow, including lint, CDC/RDC, synthesis, timing constraint development, and design‑for‑test readiness.
Partner with STA and PNR teams to support timing closure, floorplanning, congestion analysis, and design optimizations across advanced process nodes.
Lead integration of digital logic into larger subsystems and top‑level assemblies, ensuring clean interfaces, modularity, and reusability.
Develop scalable and maintainable design components, including parameterized datapaths, DSP building blocks, and reusable infrastructure logic.
Work closely with DV teams to define verification strategies, review test plans, and ensure functional, coverage‑driven, and power‑aware validation of the design.
Support pre‑silicon validation, including emulation, FPGA prototyping, and performance modeling of high‑speed datapaths and DSP algorithms.
Drive post‑silicon bring‑up and debug, collaborating with lab and systems teams to validate functionality, characterize performance, and resolve complex issues across datapath, DSP, and protocol layers.
Participate in detailed design and micro‑architecture reviews, contributing to continuous improvement of design, verification, and methodology flows.