Hardware Design Engineering, Director - OEM, Silicon Validation Platforms & Rack-Scale Design - Taiwan

What you'll do

• Taiwan Engineering Center Leadership
• Establish, build, and lead Astera Labs' Taiwan hardware engineering center as the company's primary Asia-based hub for OEM engagement, silicon platform design, and rack-scale product development
• Recruit, hire, and develop a high-caliber multidisciplinary engineering team in Taiwan, including:
• Hardware/PCB design engineers
• Mechanical engineers
• Validation engineers
• Customer/applications hardware engineers
• Lab engineers
• Define organizational structure, hiring roadmap, and operating model for the Taiwan center — balancing local autonomy with global alignment
• Establish lab infrastructure in Taiwan to support silicon platform bring-up, customer demonstrations, OEM design reviews, interoperability testing, and rack-scale system validation
• Drive engineering culture that emphasizes customer responsiveness, design excellence, and tight collaboration with Santa Clara headquarters
• Serve as the senior Astera Labs engineering leader in Asia — representing the company with customers, partners, and industry stakeholders in the region
• OEM Design Enablement & Customer Engagement
• Customer Design Support:
• Serve as the primary hardware engineering interface for OEM customers in Asia who are designing Astera Labs silicon (retimers, re-drivers, connectivity ASICs) into their own products
• Provide expert-level design review support for customer hardware designs — reviewing schematics, PCB layouts, stackups, power delivery networks, thermal solutions, and signal integrity
• Deliver hands-on technical engagement during customer design cycles — from initial architecture consultation through prototype bring-up, debug, and production readiness
• Support customer hardware debug and troubleshooting when integration challenges arise — coordinating across internal teams (silicon, firmware, SI, validation) to provide rapid root-cause analysis and corrective guidance
• Travel to customer sites across Asia (Taiwan, China, Japan, Korea) to provide on-site design review, bring-up support, and integration assistance for critical programs
• Reference Design & Design Collateral Development:
• Develop and maintain production-quality reference designs for Astera Labs silicon — including reference schematics, recommended PCB layouts, stackup guidelines, power delivery reference circuits, and thermal design examples
• Create comprehensive hardware design guides, integration manuals, application notes, and best-practice documentation that enable OEM customers to achieve first-pass success
• Develop design review checklists and self-assessment tools for OEM customers, supplemented by Astera Labs expert review at critical milestones
• Ensure reference designs and collateral evolve with each silicon generation and incorporate lessons learned from customer engagements
• OEM Relationship Management:
• Build deep, trust-based technical relationships with hardware engineering teams at key OEM customers — becoming their preferred technical partner for Astera Labs silicon integration
• Partner with Sales, FAE, and Product Management teams to identify high-value customer engagements and prioritize hardware engineering support resources
• Participate in customer roadmap discussions, providing hardware engineering perspective on future silicon requirements, package options, and platform integration considerations
• Capture common customer design challenges, failure modes, and feature requests — feeding these back into reference designs, design guides, evaluation platforms, and silicon requirements
• Support joint development programs with strategic OEM partners — including co-designed products, custom form factors, and platform-specific optimizations
• Silicon Validation Platform Design (SVB/EVB)
• Platform Architecture & Design:
• Own the architecture, design, and delivery of Silicon Validation Boards (SVB) and Evaluation Boards (EVB) for all Astera Labs silicon products — retimers, re-drivers, PCIe/CXL switches, and connectivity ASICs
• Design complex multi-layer PCBs optimized for silicon bring-up, characterization, and performance demonstration — including high-speed channel routing, configurable topology options, comprehensive power delivery, and debug/instrumentation access
• Ensure evaluation platforms provide optimal silicon exercising capability — enabling full characterization of all silicon features, performance modes, and operational corners
• Design platforms that serve dual purposes: internal silicon validation and external customer evaluation/demonstration
• Create modular, scalable platform architectures that can be efficiently adapted across silicon generations with minimal redesign
• Silicon Bring-Up & Characterization Support:
• Partner with silicon design and validation teams to ensure SVB/EVB designs support all required bring-up sequences, test modes, and characterization scenarios
• Support initial silicon bring-up activities on new platforms — providing hardware debug expertise and rapid board-level modifications as needed
• Ensure platform designs enable comprehensive performance characterization — including high-speed link testing, power measurement, thermal characterization, and margin analysis
• Design instrumentation access (probe points, headers, measurement interfaces) that enables efficient silicon debug without compromising signal integrity
• Customer Evaluation Enablement:
• Design evaluation platforms that provide customers a compelling, easy-to-use experience for evaluating Astera Labs silicon in their target applications
• Include customer-relevant interfaces, connectors, and configurations that match real deployment scenarios (OSFP, QSFP-DD, PCIe/CXL slots, network interfaces)
• Develop evaluation platform documentation including user guides, quick-start instructions, test procedures, and application examples
• Support customer evaluation activities — providing technical guidance, interpreting results, and facilitating customer design-in decisions
• Rack-Scale Product Design
• Chassis & System-Level Design:
• Lead the hardware design of rack-scale products including AI chassis-class systems, switch trays, CEM cards, and integrated connectivity platforms
• Own system-level architecture decisions — including backplane/midplane topology, slot configurations, power distribution architecture, cooling strategy, and management interfaces
• Design high-density backplane/midplane PCBs with high-speed interconnect routing supporting 112G/224G PAM4 signaling
• Drive power distribution design for rack-scale systems — including AC/DC conversion, point-of-load regulation, power sequencing, hot-swap protection, and power budgeting
• Design BMC/management subsystems for chassis products — including platform monitoring, thermal management, fault detection, and remote management interfaces
• Mechanical & Thermal Design:
• Direct mechanical engineering for rack-scale products — chassis sheet metal, card cages, cable management, hot-swap mechanisms, rack mounting, and serviceability
• Drive thermal/airflow architecture for chassis systems — including fan tray design, airflow optimization, thermal sensor placement, and thermal throttling strategies
• Evaluate and integrate liquid cooling solutions for high-power-density rack-scale AI infrastructure applications
• Ensure mechanical designs comply with relevant rack standards (OCP, Open19, EIA-310) and customer-specific mechanical requirements
• ODM Collaboration:
• Partner with ODM manufacturers in Asia for chassis and system-level products — providing design specifications, reviewing ODM designs, and driving joint development
• Manage technical ODM relationships for rack-scale products, navigating the differences from traditional CM engagement models
• Conduct design reviews of ODM-proposed solutions, ensuring alignment with Astera Labs' performance, quality, and reliability requirements
• Leverage proximity in Taiwan to maintain close, high-cadence collaboration with ODM engineering teams
• Hardware Validation (Platform & Rack-Scale)
• Define and execute validation strategies for silicon evaluation platforms and rack-scale products — ensuring comprehensive coverage across electrical performance, signal integrity, power delivery, thermal behavior, mechanical integrity, and environmental reliability
• Establish validation methodologies specific to evaluation platforms — including silicon interface verification, channel characterization correlation, power delivery accuracy, and instrumentation validation
• Drive rack-scale product validation including system-level thermal testing, power stress testing, mechanical shock/vibration, EMC/EMI compliance, and safety certification
• Support interoperability testing between rack-scale products and the broader ecosystem of host platforms, NICs, switches, and cables
• Build validation infrastructure in Taiwan that enables local execution of the majority of validation activities without dependency on Santa Clara labs
• Cross-Functional Collaboration
• With Santa Clara HQ:
• Maintain tight alignment with the Senior Director of Hardware Design Engineering and peer engineering leaders on technology roadmap, design standards, and resource priorities
• Collaborate with AEC/SCM hardware design teams to ensure consistency in design methodologies, component strategies, and validation approaches
• Partner with Signal Integrity engineering on channel modeling, simulation-to-measurement correlation, and design rule development
• Coordinate with Firmware Engineering on hardware-firmware co-design for evaluation platforms and rack-scale products (power sequencing, BMC, CMIS, diagnostics)
• With Manufacturing & NPI:
• Partner with Manufacturing Engineering and NPI teams to ensure silicon platforms and rack-scale products are manufacturable, testable, and scalable
• Leverage Taiwan proximity to CM/ODM sites to drive efficient DFM/DFA reviews, pilot builds, and production ramp support
• Participate in make-vs-buy decisions for rack-scale products — evaluating internal design vs. ODM engagement for each product
• With Product Management & Sales:
• Align silicon platform and rack-scale product development priorities with product management roadmap and customer demand
• Partner with Sales and FAE teams to prioritize OEM engagements and allocate customer hardware engineering resources
• Provide technical input for customer proposals, RFQ responses, and competitive evaluations
• Represent hardware engineering in customer-facing executive discussions and technical reviews
• Lab Infrastructure (Taiwan)
• Define and build the Taiwan lab environment to support:
• Silicon evaluation platform bring-up and characterization (high-speed oscilloscopes, BER testers, VNAs, power analyzers)
• Rack-scale system test (power load testing, thermal chambers, airflow measurement, EMC pre-compliance)
• Customer demonstration and interoperability testing
• OEM customer joint debug sessions
• Drive capital equipment planning and procurement for the Taiwan lab
• Ensure lab capabilities enable the Taiwan team to operate with high autonomy while maintaining measurement correlation with Santa Clara labs
• Basic Qualifications
• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline
• 15+ years of progressive experience in hardware design engineering for high-speed interconnect, server/switch systems, silicon evaluation platforms, or data center infrastructure products
• 5+ years in engineering management/leadership roles, including building and leading multi-team hardware engineering organizations
• Proven track record designing complex high-speed PCBs at 56G/112G PAM4 data rates or above — including evaluation boards, system boards, or backplane/midplane designs
• Demonstrated experience engaging with OEM customers on hardware design enablement, design reviews, and technical support for silicon/ASIC integration
• Strong background in silicon evaluation platform (EVB/SVB) design — enabling bring-up, characterization, and customer evaluation of complex semiconductor products
• Experience with rack-scale or chassis-class system design — including power distribution, thermal management, backplane design, and mechanical packaging
• Deep understanding of signal integrity, power delivery network design, thermal management, and high-speed PCB design best practices
• Proven ability to build engineering teams and establish new engineering site operations
• Experience working with ODM partners and contract manufacturers in Asia
• Excellent communication skills in both English and Mandarin (or other relevant Asian languages)
• Based in Taiwan (Hsinchu or Taipei area) with willingness to travel across Asia (China, Japan, Korea) and to US headquarters regularly