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Lead the verification of complex IPs and SoC subsystems from specification through tape-out.

Develop comprehensive verification plans based on architectural and functional specifications.

Own verification execution, coverage closure, regression management, and verification sign-off.

Drive verification milestones while ensuring quality and schedule commitments.

Verification Development

Design and develop scalable UVM/SystemVerilog verification environments.

Develop reusable verification components including agents, drivers, monitors, scoreboards, assertions, and coverage models.

Create constrained-random and directed test scenarios to verify functionality and corner cases.

Drive functional and code coverage closure.

Protocol Verification

Verify one or more of the following protocols:

Compute Express Link (CXL)

PCI Express (Gen4/Gen5/Gen6)

Ethernet (10G/25G/50G/100G/200G/400G)

AXI, APB, AHB

High-speed SerDes interfaces

DDR/LPDDR/HBM interfaces (preferred)

Debug & Quality

Debug RTL, protocol, and integration issues using simulation and waveform analysis.

Develop SystemVerilog Assertions (SVA) and protocol checkers.

Analyze regression failures and drive root-cause resolution with Design teams.

Ensure verification completeness and high-quality tape-out readiness.

Cross-Functional Collaboration

Work closely with Architecture teams to review specifications and verification requirements.

Partner with RTL designers during implementation and debug.

Collaborate with Firmware, Validation, Emulation, and Post-Silicon teams to support product bring-up.

Participate in architecture, design, and verification reviews.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
6–12+ years of experience in Design Verification.
Strong expertise in SystemVerilog and UVM.
Experience developing constrained-random, coverage-driven verification environments.
Strong understanding of digital design fundamentals and computer architecture.
Hands-on experience with assertions (SVA), functional coverage, and verification sign-off.
Strong debugging skills using simulation tools and waveform analysis.
Experience with Synopsys VCS, Cadence Xcelium, or Siemens Questa simulators.

Nice to have

Experience verifying CXL, PCIe, Ethernet, or other high-speed connectivity protocols.
Knowledge of SoC verification methodologies and subsystem integration.
Familiarity with cache coherency and high-speed interconnects.
Experience with Formal Verification, CDC/RDC verification, and low-power verification.
Knowledge of scripting languages such as Python, Perl, Tcl, or Shell.
Experience with CI/CD pipelines and regression automation.
Exposure to emulation or FPGA-based verification is a plus.
Verification experience on networking, connectivity, storage, or AI accelerator SoCs.
Experience delivering multiple successful silicon tape-outs.
Working knowledge of AI infrastructure or data center technologies.
Ability to independently lead verification efforts for complex IPs or SoC subsystems.
Why Astera Labs?
At Astera Labs, you'll help build the connectivity solutions that power the world's most advanced AI and cloud platforms. You'll work on cutting-edge technologies, collaborate with exceptional engineers, and have the opportunity to influence products that are shaping the future of accelerated computing. If you're passionate about solving complex verification challenges and delivering world-class silicon, we'd love to hear from you.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Tech stack

PythonPerlCi/cd

About the role

What you'll do

Requirements

Nice to have

Tech stack