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Physical Design for PPA Optimization Engineer at Intel · Trevo
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Job Description
About the role
Job Details:
Our team is dedicated to optimizing Intel’s cutting-edge process technology to meet the rapidly evolving needs of next-generation silicon designs. Operating at the intersection of process and design development, we drive continuous innovation in both physical design and methodology. We partner closely with Core and SoC design teams worldwide to drive both process and product-level optimization - directly enabling Intel to deliver highly competitive, high-performance and low-power products.
Role Overview
As a Physical Design & PPA Optimization Engineer, you will play a key role in achieving best-in-class Power, Performance, and Area (PPA) for Intel IPs. You will be responsible for identifying optimization opportunities, developing physical design optimization methodologies, executing the full physical design flow to evaluate PPA landing zones on new Intel process technologies, and translating findings into actionable recommendations that influence strategic decision-making and product direction.
What you'll do
Define and implement DTCO experiments to evaluate the interaction between process technology and physical design implementation.
Define and develop design optimization methodologies across all physical design flow domains, such as placement, CTS, routing, and timing closure
Run the full PnR flow to evaluate new technology impacts on PPA metrics.
Identify trade-offs and optimization opportunities at the device, cell, and block
Requirements
BSc or MSc in Electrical Engineering, Computer Engineering, or a related field
Hands-on experience in physical or circuit design
Basic scripting experience using Python, Tcl, or a similar language
Strong analytical and problem-solving skills
Ability to analyze implementation results and communicate conclusions clearly
Nice to have
2+ years of experience in physical design or circuit design
Familiarity with physical design implementation flows and methodologies
Solid understanding of transistor, cell, and block-level PPA trade-offs
Experience developing physical design methodologies and analysis tools
Job Type:
Experienced Hire
Shift:
Shift 1 (Israel)
Primary Location:
Israel, Haifa
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.