We use PostHog and Clarity to improve the site, and Meta Pixel to measure page views and ad effectiveness. Usage data may include page addresses and browser identifiers. You can opt out of collection at any time. Details in the Privacy Policy
More fit checks, tailored CVs, and complete prep for every role.
Job Description
About the role
In most instances, this position requires in-person interviews as part of the hiring process.
What you'll do
Lead end-to-end signal integrity definition, channel budgeting, and stackup optimization for complex multi-die packages, including 2.5D (CoWoS, EMIB, InFO), 3D vertical stacking, and high-density organic substrates.
Architect and optimize multi-terabit interconnects across Die-to-Die (UCIe/BoW), host links (PCIe Gen6/7, PAM4/# SerDes), and memory subsystems (HBM3/4, DDR5, LPDDR6) in close collaboration with PHY and silicon design teams.
Build high-accuracy 3D full-wave electromagnetic models (HFSS) for micro-bumps, C4 bumps, TSVs, interposers, and BGA transitions, establishing automated flows for statistical eye/BER margin analysis.
Define high-frequency test vehicles, fixtures, and measurement methodologies; execute multi-port VNA, TDR, and real-time scope characterizations to correlate lab measurements with predictive simulations.
Collaborate closely with Silicon Design, Package Layout, Board/System, and external foundry/OSAT partners to resolve design trade-offs
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Nice to have
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in Signal Integrity (SI), Power Integrity (PI), or high-speed hardware packaging.
Experience in electrical channel modeling, jitter budgeting, and return loss/crosstalk optimization for high-speed serial or parallel interfaces (e.g., PCIe Gen5/6, SerDes PAM4, DDR5, or Die-to-Die interconnects).
Experience with lab measurement equipment, including multi-port Vector Network Analyzers (VNA), Time-Domain Reflectometry (TDR), and high-bandwidth real-time oscilloscopes for simulation correlation.
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience leading SI/PI technical architecture for server-class CPUs, high-performance AI accelerators (TPUs/GPUs), or multi-chiplet modules (MCM).
Experience developing automated EM extraction, layout parsing, and high-throughput statistical eye/BER margin analysis pipelines using Python, MATLAB, or Tcl.
Ability to lead cross-functional technical teams, mentor engineers, and drive technical roadmaps with external OSATs, substrate manufacturers, and foundries.
About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.