About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Center of Excellence (COE), part of the Custom Cloud Solutions (CCS) Business Unit within Marvell's Data Center Group, is chartered to define,
develop, and maintain standard, production-ready IP subsystems — spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and
other critical technologies — that customers and internal SoC teams can adopt with confidence.
By shifting left, the COE enables faster time-to-market, reduces integration risk, and ensures compliance, interoperability, and high performance across
Marvell's SoC products. It embodies the "One Marvell" principle — sharing reusable components, verification environments, and knowledge across all
business units to drive first-pass-right silicon.
As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering Marvell's most advanced custom chips for hyperscale
cloud, AI, and data center customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation.
What You Can Expect
Own and drive DDR/LPDDR/HBM subsystem micro-architecture definition, RTL implementation, and integration
Collaborate closely with Architecture teams to translate requirements into robust RTL designs
Work with Design Verification teams on test-plan reviews, debug, and coverage closure
Partner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL
Support silicon bring-up and post-silicon debug, working with firmware and validation teams
Drive design quality improvements, coding best practices, and reuse across projects
Participate in design reviews, milestone reviews, and cross-functional technical discussions
Mentor junior designers and provide technical leadership within the DDR/LPDDR/HBM design domain