Job Details:
About the team:
Network and Collectives owns the scale-out communication substrate for our AI accelerator - the NCCL equivalent for our hardware. We turn many chips into one machine: all-reduce, all-gather, reduce-scatter and point-to-point, made topology-aware and mapped onto the rack/pod interconnect.
We are measured on real fabric across a pod, not on a single card, and we pair tightly with the Tray/Rack/Pod/Cluster HW pillar and the Multi-Node Runtime team.
עיקרי התפקיד
Design and implement collective algorithms tuned to our interconnect topology and bandwidth/latency profile.
Build a topology-aware transport layer over the tray/rack/pod.
Optimize end-to-end collective performance across multi-node pods; profile, find bottlenecks, and close the gap to fabric peak.
Co-design with HW on interconnect features, and with Multi-Node Runtime on partitioning, overlap, and scheduling.
Own correctness and numerical determinism of reductions across scale-out.
דרישות
5+ years AI/Systems/HPC software in C++; strong concurrency and lock-free design.
Hands-on with collective libraries (NCCL/MPI/etc) or scale-out communication.
Working knowledge of the communication patterns behind tensor, pipeline, and expert parallelism, and how they map onto collectives and the underlying fabric.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.