•; Define and develop simulation and verification environments (testbenches and frameworks) for complex SoC designs.
• Support RTL development and full-chip integration through verification planning, test writing, and debugging.
• Analyze and resolve functional issues discovered during simulation or integration phases.
• Drive continuous improvement in verification methodologies and flows.
• Collaborate cross-functionally to align with architecture and design specifications.
דרישות:
• B.Sc. in Electrical Engineering from a recognized university.
• Minimum of 3 years of hands-on experience in ASIC/FPGA verification
• Strong knowledge in verification methodologies, simulation tools, and debugging.
• Excellent communication and teamwork skills — ability to thrive in a fast-paced, collaborative environment.
• Advantageous Experience:
o Experience with Specman/e.
o Familiarity with UVM (Universal Verification Methodology).
ניסיון נדרש: 3-4 שנים