Senior Staff Analog Mixed-Signal Design Engineer

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell's Central Engineering organization provides the most advanced and key analog IPs to all businesses within Marvell. You’ll be part of a key analog team that makes an outsized impact not only for the organization but also to the technological arc of innovation for future generations of Marvell's high-speed wireline and optical products. What You Can Expect Design and develop high-speed and low-power analog mixed-signal circuits in advanced CMOS technologies, with a focus on SerDes (Serializer/Deserializer) die-to-die communication and high-speed wireline design. Design of analog mixed-signal blocks such as: Clock Generation and Distribution, DLLs, Custom high-speed digital circuits, CTLE, VGA, TX Drivers, ADCs, DACs, and Regulators. Supervise and guide layout activities to ensure design accuracy and performance. Conduct post-silicon testing and validation of analog mixed-signal circuits. Collaborate with cross-functional teams to ensure successful project execution. Utilize state-of-the-art EDA tools for design automation and verification. Prepare and maintain detailed documentation of design processes and results. Prepare and participate in design reviews to ensure design quality and compliance with project requirements. What We're Looking For MS/PhD in Electrical Engineering and 7+ years of demonstrated experience in analog mixed-signal design, specifically in one or more of the following areas: ADC, DAC, voltage regulators, clock generation and distribution circuits, DLLs, custom high-speed digital circuits, CTLE, VGA, and TX drivers. Expertise in high-speed and low-power design within advanced CMOS technologies, including knowledge of trade-offs and optimization techniques for performance and power efficiency. Ability to identify, analyze, and resolve complex design issues, ensuring robust and reliable circuit performance. Experience in overseeing layout engineers, providing guidance on best practices, and ensuring that layout designs meet performance, area, and reliability requirements. Experience in post-silicon validation, including hands-on experience with lab equipment, debugging, and characterization of analog mixed-signal circuits. Good understanding of CMOS process technology, device physics, and the impact of process variations on circuit performance. Proficient in using electronic design automation (EDA) tools for schematic capture, simulation, layout, and verification, such as Cadence, Synopsys, or Mentor Graphics Strong communication, presentation and documentation skills. Expected Base Pay Range (USD) 147,830 - 221,400, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-TD1