Hardware Design Engineer

Description Nexite develops next-generation retail IoT infrastructure for retail industry. We are looking for a hands-on Hardware Design Engineer to own the full hardware lifecycle — schematic capture, PCB layout, mixed signal circuit design, power architecture, bring-up, and regulatory certification — across current and next-generation hardware. Responsibilities Digital Hardware Design — MCU, PHY, Ethernet & PoE • Design the complete digital hardware stack: NXP i.MX RT MCU schematic and BGA layout, Ethernet PHY circuit and controlled-impedance Ethernet routing. Design and validate the IEEE 802.3af PoE front-end : PD handshake, mid/end-span bridge rectifiers, isolated flywheel buck , and optocoupler feedback regulation; analyse cross-domain IO level margins across all MCU interfaces to confirm safe driver/receiver operation. RF & Analog Circuit Design • Design the ISM transmit chain and 2.4 GHz AoA receive chain; simulate match networks with ADS or equivalent and validate with VNA S-parameter measurements. PCB Design & Layout • PCB layout: Define stack-up and controlled-impedance rules; route high pin-count BGAs and high-speed peripherals with length tuning; partition RF, digital, and power domains for FCC/ETSI compliance. • Power, calibration & test: Design DCDC/LDO supplies and power distribution; define hardware test procedures for RF power and frequency calibration at production. Production Support • Failure analysis (field & manufacturing) • Yield improvement • Cost reduction Post-Silicon Verification Support Requirements • B.Sc. in Electrical Engineering – mixed-signal focus. • 3-5 years of hands-on PCB design experience for production hardware of analog and digital design, including 2 years with RF circuits at 900 MHz and/or 2.4 GHz. • Proficiency in Altium Designer or OrCAD/Allegro for multi-layer high-density layout: controlled impedance, differential pairs, and RF routing. • Experience with multi-domain power architectures: DCDC converters, LDOs, power sequencing circuits, and IO level compatibility analysis. • Experience digital hardware stack: NXP i.MX RT MCU schematic and BGA layout, Ethernet PHY circuit • Solid RF fundamentals: S-parameters, impedance matching, Smith chart, link budgets, directional couplers, as well as LNA and PA operation. • Hands on experience with lab equipment: oscilloscope, logic analyser, VNA, and spectrum analyser. • Familiarity with EMI/EMC design practices and experience supporting hardware through FCC, CE, or equivalent certification. Advantage • Experience with angle of arrival concepts (such as BLE AoA) and the associated hardware design/constraints. • Experience with NXP MCUs hardware constraints. • Experience designing PoE (IEEE 802.3af/at) and isolated flywheel buck power delivery circuits. • Experience with HyperRAM and high-speed PCB design. • Experience with Ethernet hardware design and manufacturing RF test fixtures.